Teseda V520(TM) hardware platform Start Price USD 2,000.00 Current Price USD 2,000.00 Time Left 14 days 19 hours 31 minutes Bid Count 0 Buy It Now Price - Reserve Price - Start Time Tuesday, November 25, 2008 End Time Saturday, January 24, 2009 Location Texas See more about 'Teseda V520(TM) hardware platform' Description Teseda V520(TM) hardware platform   The Teseda V520 extends the application range of our DFT-Optimized V500 Series of engineering test systems," Morris continued. "With its unique Per-Pin Timing architecture, the Teseda V520 accommodates devices with even the most strenuous DFT requirements. And, given the system's compact size and affordability, it is an ideal platform to support failure analysis of a wide range of DFT-enabled chips, accelerating the correction of yield problems." The Teseda V520's DFT-Optimized(TM) architecture provides the industry's most cost-effective test capability for DFT-enabled devices. The system occupies approximately one square foot (.1 m2) of space and weighs less than nine pounds (4 kg), and is so quiet it integrates unobtrusively in an office or lab environment. Nonetheless, with Per-Pin Timing (PPT), data rates to 50MHz, clocks to 700MHz, and a total of 348 pins with 32 million vectors behind each pin, the Teseda V520 is fully capable of handling many of the most complex chips and advanced DFT constructs.      Winning bidder to pay $20 S&H&I. Will ship to USA 48 States only.     Place a Bid!